Job Description
· Perform Design synthesis with DC synopsys, with full knowledge and understanding of functional constraints
· Create functional constraints for functional, DFT modes for synthesis by working closely with Design Engineers
· Implementation of Design for Test with latest DFT methodology for compressed scan, transition faults, RAM/ROM and other test mode requirements
· Creation of test control blocks, and test control points for test mode is essential
· Write quality Low power intent file using CPF/UPF from specification and verifying correctness of power intent file using CLP or another tools.
· Perform Logic equivalence checks
· Experience in STA/timing closure and create automatic scripts to close all timing violations
· Work with physical design engineer to resolve all netlist and timing issues
· Experience in creating ATPG pattern for high coverage with Synopsys DFT/Tetramax is essential
| Company Name Flexione Systems Private Limited |
| Locations Singapore |
| Experience 4 - 7 years |
| Key Skills USB, PCIe, SATA, SoC / ARM / AHB. VHDL, VErilog, CAD, IC |
| Education M.E/M.Tech/MS |
| Function Manufacturing/ Engineering/ R&D |
| Role Electrical Engineer |
| Industry • IT/ Computers - Software • Machinery/ Equipment Mfg. • Telecom |
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