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Job Description
Designation: Senior Design Engineer / Staff Design Engineer
Location: Pune
Experience Level: 4-8 years/8+ years of good RTL design experience.
Responsibilities: • Will be responsible for micro-architecture definition and RTL design of blocks and all other associated tasks as a designer eg: working with the verification team, defining synthesis constraints etc.
Requirements: • Overall exp 4-8 yrs/8+yrs
Should have good knowledge of the Protocol
Should have experience working with verification teams and guiding them with the verification plan
Should have been involved in atleast one Tapeout
Should have good understanding about the entire ASIC flow
Team Player
4 fields • PCIE; Security Engine Design; SATA/Serdes Design; USB Design
Desired Profile Please refer to the Job description above
Experience 3 - 8 Years
Industry Type Semiconductors, Electronics
Role Team Lead/ Technical Lead
Functional Area Embedded/EDA /VLSI/ASIC/Chip Design
Education UG - B.Tech/B.E.
PG - M.Tech, M.Sc
Location Pune/Mumbai
Keywords SoC Design, ASIC Design, RTL, Verilog, PCI Express, PCIe, Security Engine, SATA, SERDES, USB, HDMI
Contact Details : Please open contact Details page for address
Job Description
Designation: Senior Design Engineer / Staff Design Engineer
Location: Pune
Experience Level: 4-8 years/8+ years of good RTL design experience.
Responsibilities: • Will be responsible for micro-architecture definition and RTL design of blocks and all other associated tasks as a designer eg: working with the verification team, defining synthesis constraints etc.
Requirements: • Overall exp 4-8 yrs/8+yrs
Should have good knowledge of the Protocol
Should have experience working with verification teams and guiding them with the verification plan
Should have been involved in atleast one Tapeout
Should have good understanding about the entire ASIC flow
Team Player
4 fields • PCIE; Security Engine Design; SATA/Serdes Design; USB Design
Desired Profile Please refer to the Job description above
Experience 3 - 8 Years
Industry Type Semiconductors, Electronics
Role Team Lead/ Technical Lead
Functional Area Embedded/EDA /VLSI/ASIC/Chip Design
Education UG - B.Tech/B.E.
PG - M.Tech, M.Sc
Location Pune/Mumbai
Keywords SoC Design, ASIC Design, RTL, Verilog, PCI Express, PCIe, Security Engine, SATA, SERDES, USB, HDMI
Contact Details : Please open contact Details page for address
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Regards
HR Department
Indiajobsdb.comhrd@indiajobsdb.com
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